A non-volatile memory device is capable of electrically erasing and storing data and of retaining data without requiring a power supply. As such, non-volatile memory devices are widely used in a variety of fields. The non-volatile memory devices are typically classified into a NAND-type and a NOR-type. A NAND-type memory cell is normally used to store data; and a NOR-type memory cell is usually used for booting up a computing device (e.g., loading an operating system on a computing device).
A NOR-type non-volatile memory device structurally includes a plurality of memory cells each including a single transistor that is connected in parallel to one bit line. Additionally, only one memory cell transistor is connected between a drain connected by the bit line and a source connected by a common source line. The NOR-type non-volatile memory device has an advantage, in that, the current of the memory cell is high and it can be operated at high speed. However, it also has a disadvantage, in that, it is difficult to physically integrate within area confines due to the large area occupied by the contact of the bit line and by the source line.
Since a plurality of memory cells are connected in parallel to the bit line in the NOR-type non-volatile memory device, if a threshold voltage of the memory cell transistor becomes lower than a voltage (usually 0V) applied to a word line of the not-selected memory cells, a current flows between the source and the drain, regardless of the ON/OFF state of the selected memory cells. This results in an operational failure because all of the memory cells may be read during the ON state. In order to solve the aforementioned problem, a non-volatile semiconductor memory device having a structure generally called a split-gate type has been suggested.
Meanwhile, the non-volatile memory device can be classified into a flash memory device having a laminated gate structure of a FLOTOX structure, and a SONOS device where a multilayered gate insulating film is formed structurally similar to a MOS transistor. Since the gate insulating film of the SONOS device is a multilayered insulating layer for storing electric charges; and electric charges are stored in a deep level trap, the SONOS device compared to the flash memory device has excellent reliability and the writing or erasing operation can be carried out at a low voltage.
FIGS. 1A to 1C illustrate a method of fabricating a split-gate type non-volatile memory device with a conventional SONOS structure, in accordance with the prior art.
Referring FIG. 1A, after a device isolation film (not shown in FIG. 1A) is formed on a semiconductor substrate 10 to limit an active region 11, an electric charge storage layer 14, a first conductive film and a capping film 18, 20 are formed. A polysilicon layer is usually used as the first conductive film. Further, the electric charge storage layer 14 is formed by interposing an insulating film having a high trap density between a tunnel insulating film and a blocking insulating film. The electric charge storage layer 14 generally has a multilayer structure including a silicon oxide film, a silicon nitride film and a silicon oxide film (e.g., tunnel oxide—nitride—block oxide film, hereinafter, referred to as ‘ONO film’). In addition, the capping film has a structure in which a buffer layer, i.e., a silicon oxide film 18, and a hard mask layer, i.e., a silicon nitride film 20, are laminated.
A first electrode 16 having the capping film 18, 20 deposited thereon is formed on the active region 11 by sequentially patterning the capping film and the first conductive film. Thereafter, by oxidizing polysilicon at sidewalls of the first electrode 16, a sidewall insulating film 22 (sidewall oxide film) is formed. After removing the portion of the electric charge storage layer 14 formed on the active region where the first electrode 16 is not formed thereon and performing an oxidation process, a gate insulating film 24 is formed.
Next, as shown in FIG. 1B, a second conductive film 26 is conformally formed on the gate insulating film 24 (gate oxide film) and the proximate first electrodes 16. The second conductive film 26 is formed of polysilicon just like the first conductive film. Thereafter, a photoresist pattern 28 is formed on the second conductive film 26. The photoresist pattern 28 has an opening 27, which limits the active region between the proximate first electrodes 16.
Referring to FIG. 1C, the second conductive film 26 is patterned by using the photoresist pattern 28 as an etching mask to expose the active region 11 between the proximate first electrodes 16. As a result of this process, a second electrode 26a is formed that is extended to the substrate in parallel thereto from the upper part of the first electrode 16.
As known by those skilled in the art, numerous oxidation processes are required to fabricate a semiconductor device; and, especially in forming a memory transistor with a logic transistor, even more oxidation processes are required. Therefore, as the sidewall oxide film 22 formed at the sidewalls of the first electrode 16 goes through the subsequent oxidation processes, an area A appears to have a bird's beak shape as shown in FIG. 2. Further, through the subsequent oxidation processes, the bird's beak formed at the sidewall oxide film 22 makes the block oxide film formed under the first electrode 16 partially thick as shown in the area A.
In general, in the case of a SONOS device, programming/erasing operations are carried out while electrons are trapped at a deep energy level of a nitride film by hot electron injection in the vicinity of the lower corner of the first electrode and are flown out to the substrate by a Fowler-Nordheim tunneling. However, since the bird's beak formed at both sides of the first electrode makes the block oxide film of an area where the programming/erasing operations occur thick, there is a difficulty with performing programming/erasing operations.